1. Field of the Invention
The present invention relates to a method and an apparatus for evaluating the performance of multi-processing systems suited for use in the evaluation of a multi-processing system having a configuration that a plurality of processors capable of executing instructions in parallel are interconnected so as to be communicable with each other, and also to a memory medium storing a program for evaluating the same.
The performance of a multi-processing system (hereinafter called an MP system) significantly depends on the efficiency of communication among a plurality of processors or between a processor and a memory. Therefore, MP system performance is evaluated at various developing steps of design, architecture determining, tuning, etc.
To evaluate MP system performance, there are a number of methods available, from among which an appropriate one is selected in consideration of desired simulation accuracy and a simulation speed.
The present invention tries to reduce the cycle required to develop an MP system, by employing a trace-driven simulation method, which provides high simulation accuracy and a high simulation speed.
2. Description of the Related Art
In conventional trace-driven simulation for an MP system, hardware or software processing has been performed on processor-to-processor basis to sample execution-trace data of the time when communication between processors or between each of them and a memory (it may hereinafter be referred to as inter-processor communication) was carried out, based on which trace data thus sampled for each processor an MP system-dedicated simulator simulates the MP system.
This method can advantageously use trace data of actual programs, so as to verify patterns close to actual inter-processor communication as well as to perform simulation at a high speed because the trace data needs to be sampled only once.
A high accuracy simulation is expected in particular when the processors constituting the MP system are scalar processors which do not execute instructions in parallel.
If, however, each of the processors of an MP system is, for example, a super-scalar processor, which can execute a number of instructions in parallel, trace data may change dynamically because intra-processor processing proceeds even when inter-processor communication is under way.
Therefore, simulation of an MP system with trace data unchanged, may suffer from significant decreases in simulation accuracy.
If, on the other hand, a single processor-use simulator is used to improve latency between communication sections, by specifically sampling trace data for each processor in the simulation of the MP system, vast time is required for the simulation.